新闻动态 -

NEWS CENTER

XPJ(中国)

2014

2014年7月9-11日IC Compiler 1培训通知

作者：

天津滨海集成电路设计服务中心将于2014年7月9日至11日（下周三四五）三天举办synopsys公司工具软件IC Compiler 的培训课程，以帮助IC工程师进一步了解EDA工具的应用。培训由公司synopsys经验丰富工程师主讲，以讲课和实验穿插进行。欢迎各企业IC工程师报名参加。

报名方式：填写培训申请表（见附件）。

Overview

The class begins with how to load the required synthesis and physical data required by IC Compiler (data setup), followed by creating a floorplan, including power grid, to meet timing and routeability throughout the flow (design planning). The placement flow focuses on optimizing the placement and logic for timing, congestion, power, and scan-chain ordering. The CTS unit covers controlling and building clock trees and performing additional timing optimization, followed by routing of the clock nets. In the routing unit, you will learn the signal routing and optimization steps based on the Zroute mode, including concurrent via doubling and antenna fixing. The chip finishing unit includes steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and metal filling.

Every lecture is accompanied by a comprehensive hands-on lab.

Objectives

At the end of this workshop you should be able to use IC Compiler to:

• Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls

• Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure

• Perform placement and related optimizations to minimize timing violations, congestion, and power

• Analyze congestion maps and timing reports

• Perform pre-CTS power optimization

• Perform clock tree synthesis

• Analyze clock and timing results post-CTS

• Route the clock nets

• Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing

• Analyze and fix physical DRC and LVS violations

• Perform functional ECOs

• Perform chip finishing steps

• Generate output files required for final validation/verification

Audience Profile

ASIC, back-end, or layout designers who will be using IC Compiler to implement a complete physical design flow.

Prerequisites

Prior knowledge of standard-cell-based automatic place & route is not needed. An understanding of fundamental physical design concepts, including layout, standard cell, standard cell library, setup and hold timing, inputs and outputs of synthesis, floorplan, standard cell placement, congestion, clock tree, metal layer, via, and routing is helpful.

Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.

Course Outline

Day 1

• Introduction and Overview

• Data Setup and Basic Flow

• Design Planning

Day 2

• Design Planning (Lab continued)

• Placement

• Clock Tree Synthesis

Day 3

• Clock Tree Synthesis (Lab continued)